namespace XFESystem.Core; /// A copy of resources already assigned by the PCI bus, never a request to map or resize a BAR. public readonly record struct PciGpuMemoryBar( int Index, bool IsAssigned, bool IsIo, bool Is64Bit, bool IsPrefetchable, ulong Address, ulong Length); /// PCI discovery evidence. It is deliberately separate from an initialized rendering backend. public sealed record PciGpuDiscovery( string Address, ushort VendorId, ushort DeviceId, byte ClassCode, byte Subclass, bool PciExpress, int MessageInterruptCount, PciGpuMemoryBar[] Bars) { public bool IsNvidiaDisplayController => VendorId == 0x10DE && ClassCode == 0x03; /// /// Checks copied resource geometry before a future driver may map it. This does not /// initialize GSP firmware, an address space, a GPU channel, or the CUDA driver ABI. /// public string ValidateRegisterWindow() { if (!IsNvidiaDisplayController) return "Not an NVIDIA display controller."; if (!PciExpress) return "PCI Express capability is absent."; if (Bars is null || Bars.Length is 0 or > 6) return "Invalid PCI BAR snapshot."; bool registers = false; for (int i = 0; i < Bars.Length; i++) { var bar = Bars[i]; if (bar.Index is < 0 or > 5) return "Invalid PCI BAR index."; for (int previous = 0; previous < i; previous++) if (Bars[previous].Index == bar.Index) return "Duplicate PCI BAR index."; if (!bar.IsAssigned) continue; if (bar.IsIo) continue; if (bar.Address == 0 || bar.Length == 0 || bar.Length - 1 > ulong.MaxValue - bar.Address) return "Assigned memory BAR has an empty or overflowing address range."; if ((bar.Length & (bar.Length - 1)) != 0 || (bar.Address & (bar.Length - 1)) != 0) return "Assigned memory BAR is not aligned to its decoded size."; if (!bar.Is64Bit && (bar.Address > uint.MaxValue || bar.Length - 1 > uint.MaxValue - bar.Address)) return "A 32-bit memory BAR extends beyond 4 GiB."; if (bar.Index == 0 && !bar.IsPrefetchable) registers = true; } return registers ? string.Empty : "NVIDIA BAR 0 has no assigned non-prefetchable register window."; } }